Stanford, CMU, Penn, MIT, and SkyWater Technology reached a major milestone by producing the first monolithic 3D chip manufactured at a U.S. foundry, achieving the highest density of 3D chip wiring to date and delivering speed improvements of an order of magnitude.

Engineers from Stanford University, Carnegie Mellon University, the University of Pennsylvania, and the Massachusetts Institute of Technology have partnered with SkyWater Technology, the largest U.S.-based pure-play semiconductor foundry, to create a new type of multilayer computer chip. The design points toward major advances in artificial intelligence hardware and strengthens efforts to expand domestic semiconductor manufacturing.

Unlike conventional 2D chips that spread components across a single flat surface, the new prototype stacks extremely thin layers of circuitry on top of one another. Vertical connections link these layers, allowing data to move quickly between memory and computing elements.

This dense network of vertical wiring, combined with tightly integrated memory and processing units, helps overcome long-standing limits that have slowed progress in flat chip designs. Tests and simulations show that the 3D chip delivers performance improvements of roughly an order of magnitude compared with traditional 2D chips.

Although research groups have previously demonstrated experimental 3D chips, this is the first example to show clear performance gains while also being produced in a commercial foundry. “This opens the door to a new era of chip production and innovation,” said Subhasish Mitra, the William E. Ayer Professor in Electrical Engineering and professor of computer science at Stanford University, and principal investigator of the study presented at the 71st Annual IEEE International Electron Devices Meeting (IEDM). “Breakthroughs like this are how we get to the 1,000-fold hardware performance improvements future AI systems will demand.”

The challenges for flat chips

Modern artificial intelligence systems such as ChatGPT and Claude rely on the rapid movement of enormous volumes of data between memory, where information is stored, and computing units, where it is processed.

On standard 2D chips, these components are laid out across a single plane with limited nearby memory. As a result, data must travel along a small number of long, congested pathways. While the computing elements operate at very high speeds, data transfer cannot keep up, and insufficient local memory forces repeated delays. Engineers refer to this fundamental limitation as the “memory wall,” where processing capability exceeds the chip’s ability to supply data efficiently.

For decades, chipmakers addressed the memory wall problem by shrinking transistors – the tiny switches on a chip that perform computations and store data – and squeezing more of them onto each chip. But that strategy, too, is approaching hard, physical limits, which researchers refer to as the “miniaturization wall.”

The new chip climbs these walls by literally rising above them. “By integrating memory and computation vertically, we can move a lot more information much quicker, just as the elevator banks in a high-rise let many residents travel between floors at once,” said Tathagata Srimani, assistant professor of electrical and computer engineering at Carnegie Mellon University, the paper’s senior author, who began the work as a postdoctoral fellow advised by Mitra.

“The memory wall and the miniaturization wall form a deadly combination,” said Robert M. Radway, assistant professor of electrical and systems engineering at the University of Pennsylvania and a co-author of the study. “We attacked it head-on by tightly integrating memory and logic and then building upward at extremely high density. It’s like the Manhattan of computing – we can fit more people in less space.”

How the new 3D chip is made

Until now, most attempts at 3D chips have relied on stacking separate chips. That approach works, but the connections between layers are coarse, sparse, and prone to bottlenecks.

Instead of fabricating separate chips and then fusing them, the team builds each layer directly on top of the last in one continuous process. This “monolithic” method uses temperatures low enough to avoid damaging the circuitry below, allowing the researchers to stack components more tightly and connect them far more densely.

Perhaps even more notably, the process was completed entirely in a domestic commercial silicon foundry. “Turning a cutting-edge academic concept into something a commercial fab can build is an enormous challenge,” said co-author Mark Nelson, vice president of technology development operations at SkyWater Technology. “This shows that these advanced architectures aren’t just possible in the lab – they can be produced domestically, at scale, which is what America needs to stay at the forefront of semiconductor innovation.”

The chip’s performance and potential

Early hardware tests show that the prototype already outperforms comparable 2D chips by roughly a factor of four. Simulations of taller, future versions – with more stacked layers of memory and compute – point to even greater gains. Designs with additional tiers show up to a twelve-fold improvement on real AI workloads, including those derived from Meta’s open-source LLaMA model.

Most strikingly, the researchers say the design opens a realistic path to 100- to 1,000-fold improvements in energy-delay product (EDP), a key metric that balances speed and energy efficiency. By drastically shortening data movement and adding many more vertical pathways, the chip can achieve both higher throughput and lower energy per operation, a combination long viewed as out of reach for conventional, flat architectures.

The researchers emphasize that the long-term significance of this research goes beyond performance. By proving that monolithic 3D chips can be built on U.S. soil, they say, the work establishes a blueprint for a new era of domestic hardware innovation, one in which America can design and manufacture the most advanced chips.

Just as the integrated-circuit revolution of the 1980s was fueled by students who learned to design and build chips in U.S. labs, the researchers say the shift to vertical, monolithic 3D integration will require a new generation of engineers fluent in these technologies. Through collaborations and funding sources such as the Microelectronics Commons California-Pacific-Northwest AI Hardware Hub (Northwest-AI-Hub), students and researchers are already being trained to advance American semiconductor innovation.

“Breakthroughs like this are of course about performance,” said H.-S. Philip Wong, the Willard R. and Inez Kerr Bell Professor in the Stanford School of Engineering and principal investigator of the Northwest-AI-Hub. “But they’re also about capability. If we can build advanced 3D chips, we can innovate faster, respond faster, and shape the future of AI hardware.”